65 lines
2.2 KiB
C
65 lines
2.2 KiB
C
/* ppc32le.c
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* Copyright 1984-2017 Cisco Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "system.h"
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#include <sys/types.h>
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#include <sys/mman.h>
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#include <unistd.h>
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/* NB: when sysconf isn't helpful, hardcoding data max cache line size from PowerMac G4.
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* NB: this may cause illegal instruction error on machines with smaller cache line sizes. Also, it
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* NB: will make invalidating the caches slower on machines with larger cache line sizes. */
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#define DEFAULT_L1_MAX_CACHE_LINE_SIZE 32
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static int l1_dcache_line_size, l1_icache_line_size, l1_max_cache_line_size;
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/* flushcache_max_gap is the maximum gap between unmerged chunks of memory to be flushed */
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INT S_flushcache_max_gap(void) {
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return l1_max_cache_line_size;
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}
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void S_doflush(uptr start, uptr end) {
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uptr i;
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#ifdef DEBUG
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printf(" doflush(%x, %x)\n", start, end); fflush(stdout);
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#endif
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start &= ~(l1_max_cache_line_size - 1);
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end = (end + l1_max_cache_line_size) & ~(l1_max_cache_line_size - 1);
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for(i = start; i < end; i += l1_dcache_line_size) {
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__asm__ __volatile__ ("dcbst 0, %0" :: "r" (i));
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}
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__asm__ __volatile__ ("sync");
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for(i = start; i < end; i += l1_icache_line_size) {
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__asm__ __volatile__ ("icbi 0, %0" :: "r" (i));
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}
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__asm__ __volatile__ ("sync ; isync");
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}
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void S_machine_init(void) {
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if ((l1_dcache_line_size = sysconf(_SC_LEVEL1_DCACHE_LINESIZE)) <= 0) {
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l1_dcache_line_size = DEFAULT_L1_MAX_CACHE_LINE_SIZE;
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}
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if ((l1_icache_line_size = sysconf(_SC_LEVEL1_ICACHE_LINESIZE)) <= 0) {
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l1_icache_line_size = DEFAULT_L1_MAX_CACHE_LINE_SIZE;
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}
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l1_max_cache_line_size = l1_dcache_line_size > l1_icache_line_size ? l1_dcache_line_size : l1_icache_line_size;
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}
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